1. Field of the Invention
The present invention relates to a lock determination circuit of a PLL (phase-locked loop), and in particular, a circuit for reducing power consumption of a PLL.
This application is based on patent application No. Hei 10-363576 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
FIG. 5 is a circuit diagram showing the structure of a conventional lock determination circuit of a PLL.
As shown in the figure, such a determination circuit compares two output signals, "Up" and "Down", from a phase and frequency detector Det so as to output a signal for controlling a pull-down transistor "Tr.A", so that the analog potential of Node 1 (see FIG. 5) can be changed.
In operation, the electric potential of Node 1 is gradually changed by suitably selecting the time constant determined by resistances R51 and R52 and capacitance C51.
Generally, the PLL has a function of comparing a reference clock (signal) and a comparison (i.e., feedback) clock (signal) so as to synchronize the comparison (feedback) clock with the reference clock. In addition, the PLL includes a loop filter for smoothing the detection pulse signal from the phase and frequency detector and outputting an oscillator control signal, and also includes a voltage controlled oscillator for outputting a clock signal having a predetermined frequency, by using the oscillator control signal.
In the above function the PLL, when the power supply is activated or when the reference clock is changed, a time lag is present until the lock state is realized. Therefore, in this process, it is necessary to employ a signal for monitoring the lock and unlock states, and generally, such a lock-state determining signal is controlled using an output from the phase and frequency detector.
Here, the phase and frequency detector detects the frequency/phase difference between the reference clock and comparison (feedback) clock, and outputs the detected result using the Up and Down signals.
When a frequency/phase difference exists, one of the Up and Down signals maintains the High level during a period corresponding to the difference; thus, transistor "Tr.A" is repeatedly switched to the ON state and to the OFF state in turn.
When transistor "Tr.A" is in the ON state, the electric potential of Node 1 falls with the RC time constant: R51.times.C51, while when transistor "Tr.A" is in the OFF state, the electric potential of Node 1 rises with the RC time constant: R52.times.C51.
As the lock state approaches, the High-level state of the Up/Down signal is observed sporadically and thus the Off-state period of the transistor "Tr.A" becomes longer.
When the duration of the Off state of the transistor "Tr.A" exceeds the time "R52.times.C51", then the electric potential of Node 1 gradually rises. When this electric potential becomes Vdd/2, then at last the output level of the Lock terminal (see FIG. 5) becomes High.
After the Lock terminal becomes High and thus the lock state is determined, the electric potential of Node 1 still gradually rises towards the level Vdd, that is, Node 1 has an intermediate potential for a while.
In the above method related to FIG. 5, when Node 1 has such an intermediate potential before and after the lock determination timing, a current flows for a period through the gate which is driven by the intermediate potential, thereby consuming power.